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cy7c1302dv25 9-mbit burst of two pipelined srams with qdr? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05625 rev. *h revised november 18, 2014 9-mbit burst of two pipelined srams with qdr? architecture features separate independent read and write data ports ? supports concurrent transactions 167-mhz clock for high bandwidth ? 2.5 ns clock-to-valid access time 2-word burst on all accesses double data rate (ddr) interfaces on both read and write ports (data transferred at 333 mhz) @ 167 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for ou tput data (c and c ) to minimize clock-skew and flight-time mismatches. single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion synchronous internally self-timed writes 2.5 v core power supply with hstl inputs and outputs available in 165-ball fbga package (13 15 1.4 mm) variable drive hstl output buffers expanded hstl output voltage (1.4 v?1.9 v) jtag interface configurations cy7c1302dv25 ? 512 k 18 functional description the cy7c1302dv25 is a 2.5 v synchronous pipelined sram equipped with qdr? architecture . qdr architecture consists of two separate ports to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inpu ts to support write operations. access to each port is accomplished through a common address bus. the read address is latched on the rising edge of the k clock and the write address is latched on the rising edge of k clock. qdr has separate data inputs and data outputs to completely eliminate the need to ?turn-around? the data bus required with common i/o devices. accesses to the cy7c1302dv25 read and write ports are completely independent of one another. all accesses are initiated synchronously on the rising edge of the positive input clock (k). in order to maximize data thro ughput, both read and write ports are equipped with ddr interfaces. therefore, data can be transferred into the device on every rising edge of both input clocks (k and k ) and out of the device on every rising edge of the output clock (c and c , or k and k in a single clock domain) thereby maximizing performance while simplifying system design. each address location is associated with two 18-bit words that burst sequentially into or out of the device. depth expansion is accomplished with a port select input for each port. each port select allows each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c (or k or k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. for a complete list of related documentation, click here . selection guide description 167 mhz unit maximum operating frequency 167 mhz maximum operating current 500 ma
cy7c1302dv25 document number: 38-05625 rev. *h page 2 of 25 256kx18 clk a (17:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps q [17:0] control logic address register reg. reg. reg. 18 18 18 36 write 18 bws 0 vref write add. decode data reg write data reg memory array 256kx18 memory array 18 18 a (17:0) 18 18 c c bws 1 logic block diagram ? cy7c1302dv25
cy7c1302dv25 document number: 38-05625 rev. *h page 3 of 25 contents pin configurations ........................................................... 4 pin definitions .................................................................. 5 functional overview ........................................................ 6 read operations ......................................................... 6 write operations ......................................................... 6 byte write operations ................................................. 6 single clock mode .............. ........................................ 6 concurrent transactions ..... ........................................ 6 depth expansion ......................................................... 6 programmable impedance ........ .............. ........... ......... 7 application example ........................................................ 7 truth table ........................................................................ 8 write cycle descriptions ................................................. 8 ieee 1149.1 serial boundary sc an (jtag) ... ........... ...... 9 disabling the jtag feature ........................................ 9 test access port ......................................................... 9 performing a tap re set ............................................. 9 tap registers ............................................................. 9 tap instruction set ..................................................... 9 tap controller state diagram ....................................... 11 tap controller block diagram ...................................... 12 tap electrical characteristics ...................................... 12 tap ac switching characteristics ............................... 13 tap timing and test conditions .................................. 14 identification register definitions ................................ 15 scan register sizes ....................................................... 15 instruction codes ........................................................... 15 boundary scan order .................................................... 16 maximum ratings ........................................................... 17 operating range ............................................................. 17 electrical characteristics ............................................... 17 dc electrical characteristics ..................................... 17 ac electrical characteristics ..................................... 17 thermal resistance ........................................................ 18 capacitance .................................................................... 18 ac test loads and waveforms ..................................... 18 switching characteristics .............................................. 19 switching waveforms .................................................... 20 read/write/deselect sequence ............. ........... ........ 20 ordering information ...................................................... 21 ordering code definitions ..... .................................... 21 package diagram ............................................................ 22 acronyms ........................................................................ 23 document conventions ................................................. 23 units of measure ....................................................... 23 document history page ................................................. 24 sales, solutions, and legal information ...................... 25 worldwide sales and design s upport ......... .............. 25 products .................................................................... 25 psoc? solutions ...................................................... 25 cypress developer community ................................. 25 technical support ................. .................................... 25
cy7c1302dv25 document number: 38-05625 rev. *h page 4 of 25 pin configurations figure 1. 165-ball fbga (13 15 1.4 mm) pinout cy7c1302dv25 (512 k 18) 1 2 34567891011 a nc gnd/144m nc/36m wps bws 1 k nc rps nc/18m gnd/72m nc b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 vss a a a vss nc q7 d8 d nc d11 q10 vss vss vss vss vss nc nc d7 e nc nc q11 vddq vss vss vss vddq nc d6 q6 f nc q12 d12 vddq vdd vss vdd vddq nc nc q5 g nc d13 q13 vddq vdd vss vdd vddq nc nc d5 h nc vref vddq vddq vdd vss vdd vddq vddq vref zq j nc nc d14 vddq vdd vss vdd vddq nc q4 d4 k nc nc q14 vddq vdd vss vdd vddq nc d3 q3 l nc q15 d15 vddq vss vss vss vddq nc nc q2 m nc nc d16 vss vss vss vss vss nc q1 d2 n nc d17 q16 vss a a a vss nc nc d1 p nc nc q17 a a c a a nc d0 q0 r tdotckaaac aaatmstdi
cy7c1302dv25 document number: 38-05625 rev. *h page 5 of 25 pin definitions name i/o description d [17:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations . wps input- synchronous write port select, active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deasserting will deselect the write port. deselecting the write port will cause d [17:0] to be ignored. bws 0 , bws 1 input- synchronous byte write select 0, 1, active low . sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written in to the device during the cu rrent portion of the write operations. bytes not written remain unaltered. bws 0 controls d [8:0] and bws 1 controls d [17:9]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs . sampled on the rising edge of the k (read address) and k (write address) clocks for active read and write operations. these addre ss inputs are multiplexed for both read and write operations. internally, the device is organized as 512 k 18 (2 arrays each of 256 k 18). these inputs are ignored when the appropria te port is deselected. q [17:0] outputs- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read oper ations or k and k when in single clock mode. when the read port is deselected, q [17:0] are automatically three-stated. rps input- synchronous read port select, active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting will caus e the read port to be deselected. when deselected, the pending access is allowed to complete and the out put drivers are automatically three-stated following the next rising edge of the c clock. each read acce ss consists of a burst of two sequential transfers. c input-clock positive input cloc k for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input-clock negative input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board cack to the controller. see application example for further details. k input-clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [17:0] when in single clock mode. all a ccesses are initiated on the rising edge of k. k input-clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [17:0] when in single clock mode. zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. q [17:0] output impedance is set to 0.2 rq, w here rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc/18m n/a address expansion for 18m . this is not connected to the die and so can be tied to any voltage level. nc/36m n/a address expansion for 36m . this is not connected to the die and so can be tied to any voltage level. gnd/72m input address expansion for 72m . this must be tied low. gnd/144m input address expansion for 144m . this must be tied low. nc n/a not connected to the die . can be tied to any voltage level.
cy7c1302dv25 document number: 38-05625 rev. *h page 6 of 25 functional overview the cy7c1302dv25 is a synchronous pipelined burst sram equipped with both a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. these devices multiplex the address inputs in order to minimize the number of address pins required. by having separate read and write ports, the qdr-i completely eliminates the need to ?turn-around? the data bus and avoids any possible data conten tion, thereby si mplifying system design. accesses for both ports are initiated on the rising edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the ou tput clocks (c and c, or k and k when in single clock mode). all synchronous data inputs (d [17:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [17:0] ) pass through output registers controlled by the rising edge of the output clocks (c and c , or k and k when in single clock mode). all synchronous control (rps , wps , bws [1:0] ) inputs pass through input registers controlle d by the rising edge of input clocks (k and k ). read operations the cy7c1302dv25 is organized internally as 2 arrays of 256 k 18. accesses are completed in a burst of two sequential 18-bit data words. read operat ions are initiated by asserting rps active at the rising edge of the positive input clock (k). the address is latched on the rising edge of the k clock. following the next k clock rise the corresponding lower order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subsequent rising edge of c the higher order data word is driven onto the q [17:0] . the requested data will be valid 2.5 ns from the rising edge of the output clock (c and c , or k and k when in single clock mode, 167-mhz device). synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (c). this will allow for a seamless transition between devices without the insertion of wait st ates in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the same k clock rise the data presented to d [17:0] is latched into the lower 18-bit write data register provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ), the address is latched and the information presented to d [17:0] is stored into the write data register provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. when deselected, the write port will ignore all inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1302dv25. a write operation is initiated as described in the write operation section above. the bytes that are written are determined by bws 0 and bws 1 which are sampled with each set of 18-bit data word. asserting the appropriate byte write select input during the data portion of a write will allow the data being presented to be latched and written into th e device. deasserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1302dv25 can be used with a single clock mode. in this mode the device will recognize only the pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the oper ation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use th is mode of operation, the user must tie c and c high at power-up.this function is a strap option and not alterable during device operation. concurrent transactions the read and write ports on the cy7c1302dv25 operate completely independently of one another. since each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. also, reads and writes can be started in the same clock cycle. if the ports access the same locati on at the same time, the sram will deliver the most recent information associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. depth expansion the cy7c1302dv25 has a port select input for each port. this allows for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the s pecified port. deselecting a port will not affect the other port. all pending transactions (read and write) will be completed prior to the device being deselected. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) name i/o description
cy7c1302dv25 document number: 38-05625 rev. *h page 7 of 25 programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5 the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impedanc e matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq = 1.5 v. the output impedance is adjusted ev ery 1024 cycles to account for drifts in supply voltage and temperature. application example figure 2 shows two qdr-i srams used in an application. [1] figure 2. application example note 1. the above application shows 4 qdr-i being used.
cy7c1302dv25 document number: 38-05625 rev. *h page 8 of 25 truth table the truth table for cy7c1302dv25 follows. [2, 3, 4, 5, 6, 7] operation k rps wps dq dq write cycle: load address on the rising edge of k clock; input write data on k and k rising edges. l?h x l d(a+0) at k(t) ? d(a+1) at k (t) ? read cycle: load address on the rising edge of k clock; wait one cycle; read data on 2 consecutive c and c rising edges. l?h l x q(a+0) at c(t+1) ? q(a+1) at c (t+1) ? nop: no operation l?h h h d = x q = high z d = x q = high z standby: clock stopped stopped x x previous state previous state write cycle descriptions the write cycle description tabl e for cy7c1302dv25 follows. [2, 8] bws 0 bws 1 k k comments l l l?h ? during the data portion of a write sequence, both bytes (d [17:0] ) are written into the device. l l ? l?h during the data portion of a write sequence, both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] remains unaltered. h h l?h ? no data is written into the device during this portion of a write operation. h h ? l?h no data is written into the device during this portion of a write operation. notes 2. ,x = don't care, h = logic high, l = logic low ?? represents rising edge. 3. device will power-up deselected and the outputs in a three-state condition. 4. ?a? represents address location latched by the devices when transaction was initiated. a+0, a+1 represent the addresses seque nce in the burst. 5. ?t? represents the cycle at which a read/w rite operation is started. t+1 is the fi rst clock cycle succeeding the ?t? clock cy cle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c when clock is stopped. this is not ess ential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. assumes a write cycle was initiated per the truth table . bws 0 , bws 1 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
cy7c1302dv25 document number: 38-05625 rev. *h page 9 of 25 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149. 1-1900. the tap operates using jedec standard 2.5 v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which wil l not interfere with the operation of the device. test access port test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an applicatio n. tdi is connected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram on page 12 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sam ple z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identif ication register definitions table. tap instruction set eight different instructions ar e possible with the three-bit instruction register. all combinatio ns are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state.
cy7c1302dv25 document number: 38-05625 rev. *h page 10 of 25 idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction is loaded into the instruction regi ster upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to th e value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap co ntroller?s capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preloa d instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required ? that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system ou tput pins. this inst ruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bu s three-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus in to a three-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus three-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will e nable the output buffers to drive the output bus. when low, this bit will place the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? state. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bus pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1302dv25 document number: 38-05625 rev. *h page 11 of 25 tap controller state diagram the state diagram for the tap controller follows. [9] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 note 9. the 0/1 next to each state represents the value at tms at the rising edge of tck.
cy7c1302dv25 document number: 38-05625 rev. *h page 12 of 25 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range parameter [10, 11, 12] description test conditions min max unit v oh1 output high voltage i oh = ?? 2.0 ma 1.7 ? v v oh2 output high voltage i oh = ?? 100 ? a2.1?v v ol1 output low voltage i ol = 2.0 ma ? 0.7 v v ol2 output low voltage i ol = 100 ? a?0.2v v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage ?0.3 0.7 v i x input and output load current gnd ? v i ? v ddq ?5 5 ? a notes 10. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics on page 17 . 11. overshoot: v ih(ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?1.5 v (pulse width less than t cyc /2). 12. all voltage referenced to ground.
cy7c1302dv25 document number: 38-05625 rev. *h page 13 of 25 tap ac switchi ng characteristics over the operating range parameter [13, 14] description min max unit t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high 20 ? ns t tl tck clock low 20 ? ns set-up times t tmss tms set-up to tck clock rise 10 ? ns t tdis tdi set-up to tck clock rise 10 ? ns t cs capture set-up to tck rise 10 ? ns hold times t tmsh tms hold after tck clock rise 10 ? ns t tdih tdi hold after clock rise 10 ? ns t ch capture hold after clock rise 10 ? ns output times t tdov tck clock low to tdo valid ? 20 ns t tdox tck clock low to tdo invalid 0 ? ns notes 13. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 14. test conditions are specif ied using the load in tapac test conditions. tr/tf = 1 ns.
cy7c1302dv25 document number: 38-05625 rev. *h page 14 of 25 tap timing and test conditions figure 3 shows the tap timing and test conditions. [15] figure 3. tap timing and test conditions (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25 v test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov 50 ? 2.5 v 0 v all input pulses 1.25 v note 15. test conditions are specified using the load in tap ac test conditions. tr/tf = 1 ns.
cy7c1302dv25 document number: 38-05625 rev. *h page 15 of 25 identification regi ster definitions instruction field value description cy7c1302dv25 revision number (31:29) 000 version number. cypress device id (28:12) 01011010010010110 defines the type of sram. cypress jedec id (11:1) 00000110100 allows unique identification of sram vendor. id register presence (0) 1 indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/outp ut contents. places the boundary sc an register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input/o utput ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
cy7c1302dv25 document number: 38-05625 rev. *h page 16 of 25 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 27 11h 54 7b 81 3g 1 6p 28 10g 55 6b 82 2g 26n 299g 566a 831j 3 7p 30 11f 57 5b 84 2j 4 7n 31 11g 58 5a 85 3k 57r 329f 594a 863j 6 8r 33 10f 60 5c 87 2k 7 8p 34 11e 61 4b 88 1k 8 9r 35 10e 62 3a 89 2l 9 11p 36 10d 63 1h 90 3l 10 10p 37 9e 64 1a 91 1m 11 10n 38 10c 65 2b 92 1l 12 9p 39 11d 66 3b 93 3n 13 10m 40 9c 67 1c 94 3m 1411n 419d 681b 951n 15 9m 42 11b 69 3d 96 2m 16 9n 43 11c 70 3c 97 3p 17 11l 44 9b 71 1d 98 2n 18 11m 45 10b 72 2c 99 2p 19 9l 46 11a 73 3e 100 1p 20 10l 47 internal 74 2d 101 3r 21 11k 48 9a 75 2e 102 4r 22 10k 49 8b 76 1e 103 4p 23 9j 50 7c 77 2f 104 5p 24 9k 51 6c 78 3f 105 5n 25 10j 52 8a 79 1g 106 5r 26 11j 53 7a 80 1f
cy7c1302dv25 document number: 38-05625 rev. *h page 17 of 25 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .............................. ?65 c to + 150 c ambient temperature with power applied ........................................ ?55 c to + 125 c supply voltage on v dd relative to gnd .....?0.5 v to +3.6 v supply voltage on v ddq relative to gnd .... ?0.5 v to +v dd dc applied to outputs in high z .......?0.5 v to v ddq + 0.5 v dc input voltage [16] ........................... ?0.5 v to v dd + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature (t a ) v dd [17] v ddq [17] commercial 0 c to +70 c 2.5 0.1 v 1.4 v to 1.9 v electrical characteristics over the operating range dc electrical characteristics over the operating range parameter [18] description test conditions min typ max unit v dd power supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage 1.4 1.5 1.9 v v oh output high voltage note 19 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v ol output low voltage note 20 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?0.1 ma, nominal impedance v ddq ? 0.2 ? v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss ?0.2v v ih input high voltage [16] v ref + 0.1 ? v ddq + 0.3 v v il input low voltage [16, 21] ?0.3 ? v ref ? 0.1 v i x input load current gnd ? v i ? v ddq ?5 ? 5 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 ? 5 ? a v ref input reference voltage [22] typical value = 0.75 v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc ? ? 500 ma i sb1 automatic power-down current max. v dd , both ports deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc, inputs static ? ? 240 ma ac electrical characteristics over the operating range parameter description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? ? v v il input low voltage ? ? v ref ? 0.2 v notes 16. overshoot: v ih(ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?1.5 v (pulse width less than t cyc /2). 17. power-up: assumes a linear ramp from 0 v to v dd(min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 18. all voltage referenced to ground. 19. output are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? ? rq ? 350 ? . 20. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? ? rq ? 350 ? . 21. this spec is for all inputs except c and c clock. for c and c clock, v il(max) = v ref ? 0.2 v. 22. v ref(min.) = 0.68 v or 0.46 v ddq , whichever is larger, v ref(max) = 0.95 v or 0.54 v ddq , whichever is smaller.
cy7c1302dv25 document number: 38-05625 rev. *h page 18 of 25 thermal resistance parameter [23] description test conditions 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 16.7 ? c/w ? jc thermal resistance (junction to case) 2.5 ? c/w capacitance parameter [23] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 2.5 v, v ddq = 1.5 v 5 pf c clk clock input capacitance 6pf c o output capacitance 7pf ac test loads and waveforms figure 4. ac test loads and waveforms 1.25 v 0.25 v r = 50 ? 5pf all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75 v v ref = 0.75 v [24] 0.75 v under te s t 0.75 v device under te s t output 0.75 v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? 23. tested initially and after any design or process change that may affect these parameters. 24. unless otherwise noted, test conditions assume signal transition ti me of 2 v/ns, timing reference levels of 0.75 v, vref = 0 .75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 4 .
cy7c1302dv25 document number: 38-05625 rev. *h page 19 of 25 switching characteristics over the operating range parameters [25] description 167 mhz unit cypress parameter consortium parameter min max t power [26] v cc (typical) to the first access read or write 10 ? ? s cycle time t cyc t khkh k clock and c clock cycle time 6.0 ? ns t kh t khkl input clock (k/k and c/c ) high 2.4 ? ns t kl t klkh input clock (k/k and c/c ) low 2.4 ? ns t khk h t khk h k/k clock rise to k /k clock rise and c/c to c/c rise (rising edge to rising edge) 2.7 3.3 ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 2.0 ns set-up times t sa t sa address set-up to clock (k and k ) rise 0.7 ? ns t sc t sc control set-up to clock (k and k ) rise (rps , wps , bws 0 , bws 1 )0.7 ? ns t sd t sd d [17:0] set-up to clock (k and k ) rise 0.7 ? ns hold times t ha t ha address hold after clock (k and k ) rise 0.7 ? ns t hc t hc control signals hold after clock (k and k ) rise (rps , wps , bws 0 , bws 1 ) 0.7 ? ns t hd t hd d [17:0] hold after clock (k and k ) rise 0.7 ? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ? 2.5 ns t doh t chqx data output hold after output c/c clock rise (active to active) 1.2 ? ns t chz t chz clock (c and c ) rise to high z (active to high z) [27, 28] ?2.5 ns t clz t clz clock (c and c ) rise to low z [27, 28] 1.2 ? ns notes 25. unless otherwise noted, test conditions assume signal transiti on time of 2 v/ns, timing reference levels of 0.75 v, vref = 0 .75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 4 on page 18 . 26. this part has a voltage regulator that steps down the voltage internally; t power is the time power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 27. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of figure 4 on page 18 . transition is measured 100 mv from steady-state voltage. 28. at any given voltage and temperature t chz is less than t clz and, t chz less than t co .
cy7c1302dv25 document number: 38-05625 rev. *h page 20 of 25 switching waveforms read/write/deselect sequence figure 5. waveform for 2.0 cycle read latency [29, 30, 31] read read write write write nop read write nop k 12345 8 10 6 7 k rps wps a q d c c a1 a0 d10 t kh t khkh t khch t co t kl t cyc thc t sa t ha t hd t khch don?t care undefined t clz t chz tsc t kh t kl a2 a3 a4 a5 a6 t ha d11 d30 d31 d50 d51 d60 d61 t sd t hd q00 q21 q01 q20 q40 q41 t co t doh t doh t khkh tcyc 9 t sa t sd notes 29. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0 i.e., a0 + 1. 30. outputs are disabled (high z) one clock cycle after a nop. 31. in this example, if address a2 = a1 then data q20 = d10 and q21 = d11. write data is forwarded immediately as read results.t his note applies to the whole diagram.
cy7c1302dv25 document number: 38-05625 rev. *h page 21 of 25 ordering code definitions ordering information cypress offers other versions of this type of product in many differen t configurations and features. the below table contains o nly the list of parts that are currently available. for a comple te listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s represent atives and distributors. to find the office closest to you, visit us at t http://www.cypress.com/ go/datasheet/offices . speed (mhz) ordering code package diagram package type operating range 167 CY7C1302DV25-167BZC 51-85180 165-ball fbga (13 15 1.4 mm) commercial cy7c1302dv25-167bzxc 165-ball fbga (13 15 1.4 mm) pb-free temperature range: c = commercial = 0 c to +70 c x = pb-free; x absent = leaded package type: bz = 165-ball fbga speed: 167 mhz v25 = 2.5 v process technology: d ? 90 nm part identifier technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 1302 cy d v25 - 167 bz c x c 7
cy7c1302dv25 document number: 38-05625 rev. *h page 22 of 25 package diagram figure 6. 165-ball fbga (13 15 1.4 mm) bb165d/bw 165d (0.5 ball diameter) package outline, 51-85180 51-85180 *f
cy7c1302dv25 document number: 38-05625 rev. *h page 23 of 25 acronyms document conventions units of measure acronym description bws byte write select ddr double data rate fbga fine-pitch ball grid array hstl high-speed transceiver logic i/o input/output jtag joint test action group lsb least significant bit msb most significant bit nc no connect qdr quad data rate sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select symbol unit of measure c degree celsius mhz megahertz a microampere s microsecond ma milliampere mm millimeter mv millivolt mw milliwatt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1302dv25 document number: 38-05625 rev. *h page 24 of 25 document history page document title: cy7c1302dv25, 9-mbit burst of two pipelined srams wi th qdr? architecture document number: 38-05625 rev. ecn no. submission date orig. of change description of change ** 253010 see ecn syt new data sheet. *a 436864 see ecn nxr changed status from preliminary to final. updated features (changed c/c description). updated selection guide (removed 133 mhz and 100 mhz frequencies related information). updated pin definitions (updated description of c, c , updated description of zq (changed the sentence as ?alternately, this pin ca n be connected directly to v ddq , which enables the minimum impedance mode?)). updated tap ac switching characteristics (changed minimum value of t tcyc parameter from 100 ns to 50 ns, changed maximum value of t tf parameter from 10 mhz to 20 mhz, changed minimum value of t th and t tl parameters from 40 ns to 20 ns). updated maximum ratings (included maximum ratings for supply voltage on v ddq relative to gnd, changed the maximum ratings for dc input voltage from v ddq to v dd ). updated operating range (included industrial temperature range). updated electrical characteristics (updated dc electrical characteristics (updated note 17 (changed test condition from v ddq < v dd to v ddq ? v dd ))). updated ordering information (updated part numbers, replaced the package name column with package diagram). *b 2896202 03/19/2010 njy updated ordering information (removed inactive parts from the ordering information table). updated package diagram . *c 3122015 12/28/2010 njy updated ordering information (updated part numbers) and added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *d 3249352 05/05/2011 njy updated ordering information (updated part numbers). minor edits across the document. *e 3462032 12/12/2011 njy updated ordering information (updated part numbers). updated package diagram . *f 3594705 04/21/2012 njy updated operating range (removed industrial temperature range). *g 4397427 06/03/2014 prit updated package diagram : spec 51-85180 ? changed revision from *e to *f. updated in new template. completing sunset review. *h 4572829 11/18/2014 prit added related documentation hyperlink in page 1.
document number: 38-05625 rev. *h revised november 18, 2014 page 25 of 25 quad data rate sram and qdr sram comprise a new family of products developed by cypress, idt, nec, renesas and samsung. all pro ducts and company names me ntioned in this document may be the trademarks of their respective holders. cy7c1302dv25 ? cypress semiconductor corporation, 2004-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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